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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] - Rev 186

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Rev	Log message	Author	Age	Path
72	Expand configurability options of the program and data memory sizes.	olivier.girard	5119d 10h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
71	Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier.	olivier.girard	5266d 09h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
61	Update openMSP430 rtl.	olivier.girard	5298d 07h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
59	Update the FPGA projects with the latest core design updates.	olivier.girard	5300d 06h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
54	Update FPGA projects with the combinatorial loop fixed.	olivier.girard	5305d 11h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
37		olivier.girard	5334d 08h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
36	Remove old core version.	olivier.girard	5334d 09h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5344d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
26	Xilinx implementation example: - update the project directory structure. - make a local copy of the openMSP430 core to make the project self contained.	olivier.girard	5344d 17h	/openmsp430/trunk/fpga/diligent_s3board/rtl/
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5455d 13h	/openmsp430/trunk/fpga/diligent_s3board/rtl/

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