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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] - Rev 188

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74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5101d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5128d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5275d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
61 Update openMSP430 rtl. olivier.girard 5307d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5308d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5314d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
37 olivier.girard 5343d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
36 Remove old core version. olivier.girard 5343d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5353d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5353d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/

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