URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] - Rev 155

Rev	Log message	Author	Age	Path
59	Update the FPGA projects with the latest core design updates.	olivier.girard	5285d 15h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
54	Update FPGA projects with the combinatorial loop fixed.	olivier.girard	5290d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
37		olivier.girard	5319d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5319d 20h	/openmsp430/trunk/core/rtl/verilog/
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5440d 22h	/openmsp430/trunk/core/rtl/verilog/
17	Updated header with SVN info	olivier.girard	5466d 17h	/openmsp430/trunk/core/rtl/verilog/
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5501d 17h	/openmsp430/trunk/core/rtl/verilog/