URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 279

Rev	Log message	Author	Age	Path
259	Fixing or1200_defines FPU module selection defines - They are no longer needed	julius	5069d 12h	/openrisc/
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5069d 13h	/openrisc/
257	Changed or1200 supplementary manual from referring or or1200v2 to be just for the or1200 in general	julius	5069d 23h	/openrisc/
256	Linux patch update - disabled SCET driver by default	julius	5070d 18h	/openrisc/
255	Linux patch update with USB host data cache issue solved, file formatting fixed	julius	5072d 20h	/openrisc/
254	Update of Linux patch with USB driver, rename of its or1ksim config file	julius	5073d 13h	/openrisc/
253	No need to define PROTOTYPES, now DWARF 2 debugging is the default.	jeremybennett	5074d 00h	/openrisc/
252	Changes to use source and line info when DWARF debug data is available.	jeremybennett	5074d 00h	/openrisc/
251	Bug in register enum declaration fixed in or32. Bug with empty arguments to macro VEC_TA_GTY fixed. * config/or32/or32.h <enum reg_class>: CR_REGS removed from enumeration. * vec.h: All references to VEC_TA_GTY with an empty fourth argument replaced by VEC_TA_GTY_ANON with only three arguments <VEC_TA_GTY_ANON>: Created.	jeremybennett	5074d 00h	/openrisc/
250	Specify -DPROTOTYPES to work round problems with K&R style declarations in GDB testsuite.	jeremybennett	5075d 04h	/openrisc/