URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 431

Rev	Log message	Author	Age	Path
411	Improved ethmac testbench and software. Renamed some OR1200 library functions to be more generic. Fixed bug with versatile_mem_ctrl for Actel board. Added ability to simulate gatelevel modules alongside RTL modules in board build.	julius	4959d 20h	/openrisc/
410	ORPSoC: Adding README in root explaining how to build documentation, and documentation fixup so it builds properly again.	julius	4960d 20h	/openrisc/
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	4960d 20h	/openrisc/
408	ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.	julius	4961d 08h	/openrisc/
407	Update or1ksim version in toolchain script to rc2	julius	4961d 11h	/openrisc/
406	ORPmon indented files, bus, align and instruction errors vectors printf and reboot	julius	4961d 12h	/openrisc/
405	ORPmon updates - ethernet driver updates	julius	4961d 16h	/openrisc/
404	New scripts to build separate bare metal and Linux tool chains. Fixes to GDB so it builds with the Linux tool chain and uses RELA. Other minor fixes to the GCC tool chain.	jeremybennett	4961d 16h	/openrisc/
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	4962d 14h	/openrisc/
402	Further updates to the compiler	jeremybennett	4962d 19h	/openrisc/