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Rev Log message Author Age Path
419 ORPmon: Fixed interrupt routines in reset.S so they are compatible with new
GCC port (skip over redzone).
Added some defines to easily switch what is done when an error vector
is executed.
Added ability to print out EPCR when crashing.
Changed linker script back to one which doesn't skip over holes in SPI
flash memories.		 julius 4952d 22h /openrisc/
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 4952d 22h /openrisc/
417 ORPSoC re-adding doc automake files, this time not symlinks julius 4955d 19h /openrisc/
416 ORPSoC doc cleanup - removing symlinks from automake'd docs build path julius 4955d 19h /openrisc/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4955d 19h /openrisc/
414 Updates to add -mredzone and improved GCC optimizations. jeremybennett 4956d 14h /openrisc/
413 Fixed to combined bug in the assembler and linker. jeremybennett 4957d 17h /openrisc/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4959d 09h /openrisc/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 4959d 21h /openrisc/
410 ORPSoC: Adding README in root explaining how to build documentation, and
documentation fixup so it builds properly again.		 julius 4960d 21h /openrisc/

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