URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 479

Rev	Log message	Author	Age	Path
459	Add option to bld-all.sh to explicitly set control load of make, and fix typos.	julius	4922d 09h	/openrisc/
458	or1ksim testsuite updates	julius	4923d 08h	/openrisc/
457	or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again.	julius	4931d 22h	/openrisc/
456	ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default.	julius	4931d 23h	/openrisc/
455	Updated to support threads. Does require thread debugging enabled in uClibc.	jeremybennett	4936d 01h	/openrisc/
454	Updated to incorporate pthreads for Linux tool chain.	jeremybennett	4938d 03h	/openrisc/
453	Updates to support constructor/destructor initialization for uClibc.	jeremybennett	4938d 14h	/openrisc/
452	Update to define __UCLIBC__ when using the uClibc tool chain.	jeremybennett	4938d 22h	/openrisc/
451	More tidying up.	jeremybennett	4942d 18h	/openrisc/
450	Simplified (and hopefully more reliable) Ethernet MAC/PHY.	jeremybennett	4942d 22h	/openrisc/