URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 483

Rev	Log message	Author	Age	Path
463	ORPmon update	julius	4910d 00h	/openrisc/
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	4910d 06h	/openrisc/
461	Updated to be much stricter about usage.	jeremybennett	4912d 01h	/openrisc/
460	Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes.	jeremybennett	4912d 02h	/openrisc/
459	Add option to bld-all.sh to explicitly set control load of make, and fix typos.	julius	4912d 08h	/openrisc/
458	or1ksim testsuite updates	julius	4913d 07h	/openrisc/
457	or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again.	julius	4921d 21h	/openrisc/
456	ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default.	julius	4921d 22h	/openrisc/
455	Updated to support threads. Does require thread debugging enabled in uClibc.	jeremybennett	4926d 00h	/openrisc/
454	Updated to incorporate pthreads for Linux tool chain.	jeremybennett	4928d 02h	/openrisc/