URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 504

Rev	Log message	Author	Age	Path
484	Changes to make r12 call-saved and to bring wchar tests in line.	jeremybennett	4873d 23h	/openrisc/
483	Updated with new opcodes to generate random numbers and to identify us as Or1ksim.	jeremybennett	4876d 01h	/openrisc/
482	Don't hardcode tool versions in help text	olof	4877d 13h	/openrisc/
481	OR1200 Update. RTL and spec.	julius	4889d 08h	/openrisc/
480	ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.	julius	4890d 05h	/openrisc/
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	4891d 05h	/openrisc/
478	ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups.	julius	4892d 21h	/openrisc/
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	4893d 05h	/openrisc/
476	ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more.	julius	4893d 22h	/openrisc/
475	ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0.	julius	4894d 00h	/openrisc/