URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 510

Rev	Log message	Author	Age	Path
490	Updates to fix spurious test failures and register scheduling.	jeremybennett	4874d 05h	/openrisc/
489	ORPSoC sw cleanup. Remove warnings.	julius	4879d 12h	/openrisc/
488	ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added.	julius	4879d 13h	/openrisc/
487	ORPSoC main software makefile update	julius	4882d 10h	/openrisc/
486	ORPSoC updates, mainly software, i2c driver	julius	4882d 10h	/openrisc/
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	4886d 15h	/openrisc/
484	Changes to make r12 call-saved and to bring wchar tests in line.	jeremybennett	4887d 13h	/openrisc/
483	Updated with new opcodes to generate random numbers and to identify us as Or1ksim.	jeremybennett	4889d 15h	/openrisc/
482	Don't hardcode tool versions in help text	olof	4891d 03h	/openrisc/
481	OR1200 Update. RTL and spec.	julius	4902d 22h	/openrisc/