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Rev Log message Author Age Path
490 Updates to fix spurious test failures and register scheduling. jeremybennett 4879d 08h /openrisc/
489 ORPSoC sw cleanup. Remove warnings. julius 4884d 14h /openrisc/
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 4884d 15h /openrisc/
487 ORPSoC main software makefile update julius 4887d 13h /openrisc/
486 ORPSoC updates, mainly software, i2c driver julius 4887d 13h /openrisc/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4891d 17h /openrisc/
484 Changes to make r12 call-saved and to bring wchar tests in line. jeremybennett 4892d 16h /openrisc/
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 4894d 18h /openrisc/
482 Don't hardcode tool versions in help text olof 4896d 06h /openrisc/
481 OR1200 Update. RTL and spec. julius 4908d 00h /openrisc/

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