URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 529

Rev	Log message	Author	Age	Path
509	Tagging the 0.5.0rc3 release of Or1ksim	jeremybennett	4805d 03h	/openrisc/
508	Updates for Or1ksim 0.5.0rc3.	jeremybennett	4806d 02h	/openrisc/
507	Newlib libgloss board support update. Corresponding GCC port changes to support it.	julius	4811d 23h	/openrisc/
506	ORPSoC or1200 interrupt and syscall generation test	julius	4812d 22h	/openrisc/
505	OR1200 overflow detection fixup SPIflash program update or1200 driver library timer improvement	julius	4812d 22h	/openrisc/
504	ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup	julius	4829d 18h	/openrisc/
503	ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers.	julius	4830d 14h	/openrisc/
502	ORPSoC update - or1200, ethmac Xilinx fifos or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default	julius	4832d 18h	/openrisc/
501	ORPSoC or1200 mult/mac/divide unit serial arith bug fixed. ORPSoC or1200 defines now use serial divide by default	julius	4833d 19h	/openrisc/
500	ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc ML501 simulation makefile update to allow custom ELFs to be specified	julius	4833d 22h	/openrisc/