URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 532

Rev	Log message	Author	Age	Path
512	Updates for release 1.0rc3 for the OpenRISC 1000.	jeremybennett	4818d 04h	/openrisc/
511	Tagging the 0.5.1rc1 release of Or1ksim	jeremybennett	4819d 03h	/openrisc/
510	Updates for release 0.5.1rc1.	jeremybennett	4819d 03h	/openrisc/
509	Tagging the 0.5.0rc3 release of Or1ksim	jeremybennett	4819d 04h	/openrisc/
508	Updates for Or1ksim 0.5.0rc3.	jeremybennett	4820d 03h	/openrisc/
507	Newlib libgloss board support update. Corresponding GCC port changes to support it.	julius	4825d 23h	/openrisc/
506	ORPSoC or1200 interrupt and syscall generation test	julius	4826d 23h	/openrisc/
505	OR1200 overflow detection fixup SPIflash program update or1200 driver library timer improvement	julius	4826d 23h	/openrisc/
504	ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup	julius	4843d 19h	/openrisc/
503	ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers.	julius	4844d 15h	/openrisc/