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Rev Log message Author Age Path
791 Added options to configure RAM and ROM sizes. Fixed cache handling. skrzyp 4448d 02h /openrisc/
790 fixed issues with context switching, interrupts, optimizations and cleanups skrzyp 4455d 03h /openrisc/
789 ORPSoC: Patch from R Diez to make RTL sim report l.nops have equivalent formatting to those from or1ksim

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 julius 4458d 22h /openrisc/
788 or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 julius 4458d 23h /openrisc/
787 Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:

2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version.		 jeremybennett 4460d 07h /openrisc/
786 new ecos tree (tracking mainline) skrzyp 4460d 07h /openrisc/
785 We are about to upload a new tree (that has a different structure) skrzyp 4460d 08h /openrisc/
784 Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.

2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour.		 jeremybennett 4461d 22h /openrisc/
783 Initial dev directory snapshot with FSF GCC mainline jeremybennett 4475d 21h /openrisc/
782 Tags directory for GNU development tool chain. jeremybennett 4475d 21h /openrisc/

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