URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 820

Rev	Log message	Author	Age	Path
800	FreeRTOSV6.1.1 add or32_dma demo task for test dcache manuplation function add simple driver of wb_dma	filepang	4410d 09h	/openrisc/
799	FreeRTOSV6.1.1 add cache related function from u-boot from OpenRISC enable I/D cache if present	filepang	4411d 09h	/openrisc/
798	Added drivers for ethmac and sdcard_mass_storage_controller	skrzyp	4413d 18h	/openrisc/
797	testsuite: kill test processes that timeout	pgavin	4421d 23h	/openrisc/
796	Correct orpmon show_rx_buffs and show_mac_regs to use TX_BD_NUM properly.	yannv	4425d 02h	/openrisc/
795	Created or1200_rel3 branch from rev 794	olof	4425d 17h	/openrisc/
794	ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file Fixes lint warnings.	julius	4431d 03h	/openrisc/
793	Corrected Julius Baxter's email address in MAINTAINERS	jeremybennett	4442d 02h	/openrisc/
792	Added a MAINTAINERS file. 012-04-07 Jeremy Bennett <jeremy.bennett@embecosm.com> * MAINTAINERS: Added. * configure: Regenerated. * configure.ac: Updated version.	jeremybennett	4442d 02h	/openrisc/
791	Added options to configure RAM and ROM sizes. Fixed cache handling.	skrzyp	4444d 21h	/openrisc/