URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 94

Rev	Log message	Author	Age	Path
74	Toolchain script fix for ncurses header checking	julius	5206d 04h	/openrisc/
73	toolchain script error fix	julius	5206d 05h	/openrisc/
72	Toolchain install script: or1ksim location changed, few tweaks	julius	5209d 02h	/openrisc/
71	ORPSoC board builds, adding readmes	julius	5225d 08h	/openrisc/
70	ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\!	julius	5229d 13h	/openrisc/
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5229d 14h	/openrisc/
68	Fixed up a couple of Makefile things in ORPSoCv2	julius	5232d 06h	/openrisc/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5232d 08h	/openrisc/
66	Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software.	julius	5252d 06h	/openrisc/
65	ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix	julius	5256d 13h	/openrisc/