URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] - Rev 465

Rev	Log message	Author	Age	Path
445	gdbserver update to use kernel port ptrace register definitions.	julius	4998d 14h	/openrisc/
444	Changes to ABI handling of varargs.	jeremybennett	4998d 23h	/openrisc/
443	Work in progress on more efficient Ethernet.	jeremybennett	4999d 03h	/openrisc/
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	4999d 17h	/openrisc/
441	Changes for gdbserver.	jeremybennett	5000d 00h	/openrisc/
440	Updated documentation to describe new Ethernet usage.	jeremybennett	5000d 19h	/openrisc/
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	5002d 23h	/openrisc/
438	Fix to newlib header and library locations.	jeremybennett	5005d 23h	/openrisc/
437	Or1ksim - ethernet peripheral update, working much better.	julius	5008d 13h	/openrisc/
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	5009d 13h	/openrisc/