URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] - Rev 482

Rev	Log message	Author	Age	Path
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	4945d 17h	/openrisc/
461	Updated to be much stricter about usage.	jeremybennett	4947d 12h	/openrisc/
460	Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes.	jeremybennett	4947d 13h	/openrisc/
459	Add option to bld-all.sh to explicitly set control load of make, and fix typos.	julius	4947d 19h	/openrisc/
458	or1ksim testsuite updates	julius	4948d 18h	/openrisc/
457	or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again.	julius	4957d 08h	/openrisc/
456	ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default.	julius	4957d 09h	/openrisc/
455	Updated to support threads. Does require thread debugging enabled in uClibc.	jeremybennett	4961d 11h	/openrisc/
454	Updated to incorporate pthreads for Linux tool chain.	jeremybennett	4963d 13h	/openrisc/
453	Updates to support constructor/destructor initialization for uClibc.	jeremybennett	4964d 00h	/openrisc/