URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] - Rev 500

Rev	Log message	Author	Age	Path
480	ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.	julius	4959d 06h	/openrisc/
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	4960d 06h	/openrisc/
478	ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups.	julius	4961d 21h	/openrisc/
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	4962d 06h	/openrisc/
476	ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more.	julius	4962d 23h	/openrisc/
475	ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0.	julius	4963d 01h	/openrisc/
474	uC/OS-II port linker flags updated.	julius	4963d 07h	/openrisc/
473	Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux.	jeremybennett	4964d 02h	/openrisc/
472	Various changes which improve the quality of the tracing.	jeremybennett	4964d 03h	/openrisc/
471	Adding ucos-ii port.	julius	4966d 06h	/openrisc/