URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] - Rev 504

Rev	Log message	Author	Age	Path
484	Changes to make r12 call-saved and to bring wchar tests in line.	jeremybennett	4935d 10h	/openrisc/
483	Updated with new opcodes to generate random numbers and to identify us as Or1ksim.	jeremybennett	4937d 12h	/openrisc/
482	Don't hardcode tool versions in help text	olof	4939d 00h	/openrisc/
481	OR1200 Update. RTL and spec.	julius	4950d 19h	/openrisc/
480	ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.	julius	4951d 16h	/openrisc/
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	4952d 16h	/openrisc/
478	ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups.	julius	4954d 07h	/openrisc/
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	4954d 16h	/openrisc/
476	ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more.	julius	4955d 09h	/openrisc/
475	ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0.	julius	4955d 11h	/openrisc/