URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] - Rev 77

Rev	Log message	Author	Age	Path
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5350d 13h	/openrisc/
56	adding generic pll model to orpsoc	julius	5358d 15h	/openrisc/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5361d 05h	/openrisc/
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5371d 12h	/openrisc/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5389d 13h	/openrisc/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5390d 09h	/openrisc/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5404d 11h	/openrisc/
50	Adding or32_funcs.S	julius	5404d 15h	/openrisc/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5423d 05h	/openrisc/
48	Adds an initialization to keep GCC happy in jp1_ll_read_jp1.	jeremybennett	5423d 08h	/openrisc/