URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] - Rev 464

Rev	Log message	Author	Age	Path
444	Changes to ABI handling of varargs.	jeremybennett	4959d 16h	/openrisc/
443	Work in progress on more efficient Ethernet.	jeremybennett	4959d 20h	/openrisc/
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	4960d 10h	/openrisc/
441	Changes for gdbserver.	jeremybennett	4960d 16h	/openrisc/
440	Updated documentation to describe new Ethernet usage.	jeremybennett	4961d 11h	/openrisc/
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	4963d 16h	/openrisc/
438	Fix to newlib header and library locations.	jeremybennett	4966d 16h	/openrisc/
437	Or1ksim - ethernet peripheral update, working much better.	julius	4969d 06h	/openrisc/
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	4970d 06h	/openrisc/
435	ORPSoC updates OR1200 multiply/MAC/division unit update with serial multiply and divide options. Full divide not synthesizable yet. New software tests of multiply and divide functionality.	julius	4970d 07h	/openrisc/