URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [branches/] [or1200_rel3/] [rtl/] [verilog/] - Rev 855

Rev	Log message	Author	Age	Path
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5046d 12h	/openrisc/branches/or1200_rel3/rtl/verilog/
187	Or1200 sprs FPU update	julius	5096d 16h	/openrisc/branches/or1200_rel3/rtl/verilog/
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5096d 19h	/openrisc/branches/or1200_rel3/rtl/verilog/
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5096d 20h	/openrisc/branches/or1200_rel3/rtl/verilog/
151	OR1200 rel3 (added some files that were not checked-in earlier)	marcus.erlandsson	5105d 16h	/openrisc/branches/or1200_rel3/rtl/verilog/
142	added OpenRISC version rel3	marcus.erlandsson	5108d 00h	/openrisc/branches/or1200_rel3/rtl/verilog/
141	added OpenRISC version rel3	marcus.erlandsson	5108d 00h	/openrisc/branches/or1200_rel3/rtl/verilog/
10	or1200 added from or1k subversion repository	unneback	5509d 03h	/openrisc/branches/or1200_rel3/rtl/verilog/