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[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc1/] [cpu/] [or32/] - Rev 347

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Rev Log message Author Age Path
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5131d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5131d 23h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5135d 00h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
104 Candidate release 0.4.0rc4 jeremybennett 5138d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5147d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
100 Single precision FPU stuff for or1ksim julius 5147d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5153d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5167d 09h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5168d 10h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
91 Tidy up of some obsolete configuration code. jeremybennett 5180d 23h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/

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