OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc1/] [cpu/] [or32/] - Rev 403

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5126d 10h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5127d 09h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5130d 10h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
104 Candidate release 0.4.0rc4 jeremybennett 5133d 17h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5142d 11h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
100 Single precision FPU stuff for or1ksim julius 5142d 13h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5148d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5162d 18h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5163d 19h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/
91 Tidy up of some obsolete configuration code. jeremybennett 5176d 09h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.