OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc1/] [doc/] - Rev 851

Go to most recent revision

Filtering Options

Rev	Log message	Author	Age	Path
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5173d 13h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc/
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5174d 14h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc/
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5176d 13h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc/
104	Candidate release 0.4.0rc4	jeremybennett	5179d 21h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc/
101	ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c	jeremybennett	5188d 15h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc/
100	Single precision FPU stuff for or1ksim	julius	5188d 17h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc/
99	Bug in test evaluation for library fixed.	jeremybennett	5193d 15h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc/
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5194d 16h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc/
97	Updates to test the new JTAG library interface (not yet complete).	jeremybennett	5208d 22h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc/
96	Various changes which had not been picked up in earlier commits.	jeremybennett	5209d 23h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/doc/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.