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[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc2/] - Rev 403

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Rev Log message Author Age Path
127 New config option to allow l.xori with unsigned operand. jeremybennett 5116d 22h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5117d 17h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5117d 21h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/
122 Added l.ror and l.rori with associated tests. jeremybennett 5118d 17h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5118d 18h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5119d 15h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5121d 18h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5122d 18h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5122d 19h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5123d 18h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/

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