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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc3/] [cpu/] [common/] - Rev 509

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Rev Log message Author Age Path
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5142d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/common/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5143d 13h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/common/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5144d 10h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/common/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5148d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/common/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5163d 14h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/common/
100 Single precision FPU stuff for or1ksim julius 5163d 16h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/common/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5169d 16h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/common/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5183d 22h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/common/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5184d 23h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/common/
91 Tidy up of some obsolete configuration code. jeremybennett 5197d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/common/

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