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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc3/] [cpu/] [or1k/] - Rev 509

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Rev Log message Author Age Path
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5097d 23h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/
220 Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. jeremybennett 5104d 14h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5143d 15h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5144d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5163d 17h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5169d 18h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5184d 00h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5185d 02h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/
91 Tidy up of some obsolete configuration code. jeremybennett 5197d 15h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5197d 16h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/

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