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[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.1rc1/] [cpu/] - Rev 460

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Rev Log message Author Age Path
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5101d 00h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/
220 Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. jeremybennett 5107d 15h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/
202 Adding executed log in binary format capability to or1ksim julius 5113d 20h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5130d 20h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/
127 New config option to allow l.xori with unsigned operand. jeremybennett 5144d 20h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5145d 16h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5145d 20h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/
122 Added l.ror and l.rori with associated tests. jeremybennett 5146d 16h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5146d 17h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5147d 14h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/

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