OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.1rc1/] [cpu/] [or1k/] - Rev 513

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5079d 17h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/or1k/
220 Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. jeremybennett 5086d 08h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/or1k/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5125d 09h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/or1k/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5126d 06h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/or1k/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5145d 11h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/or1k/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5151d 12h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/or1k/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5165d 18h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/or1k/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5166d 20h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/or1k/
91 Tidy up of some obsolete configuration code. jeremybennett 5179d 09h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/or1k/
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5179d 10h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/cpu/or1k/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.