URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 142

Rev	Log message	Author	Age	Path
117	Updates on l.ff1, l.fl1 and l.maci.	jeremybennett	5111d 01h	/openrisc/trunk/
116	Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time.	jeremybennett	5111d 01h	/openrisc/trunk/
115	Added support for l.fl1 and tests for l.ff1 and l.fl1	jeremybennett	5112d 01h	/openrisc/trunk/
114	l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR.	jeremybennett	5112d 02h	/openrisc/trunk/
113	Updates to exception handling for l.add and l.div	jeremybennett	5113d 01h	/openrisc/trunk/
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5113d 01h	/openrisc/trunk/
111	Changed conditionals for Verilator to "verilator" instead of "VERILATOR".	jeremybennett	5113d 05h	/openrisc/trunk/
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5114d 02h	/openrisc/trunk/
109	or_debug_proxy does signals with signals, just ignores signals	julius	5114d 10h	/openrisc/trunk/
108	Updated to clarify overflow and exceptions for l.add, l.addc, l.addi, l.addic, l.div and l.divu.	jeremybennett	5116d 00h	/openrisc/trunk/