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[/] [openrisc/] [trunk/] - Rev 435

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Rev	Log message	Author	Age	Path
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	4957d 03h	/openrisc/trunk/
414	Updates to add -mredzone and improved GCC optimizations.	jeremybennett	4957d 23h	/openrisc/trunk/
413	Fixed to combined bug in the assembler and linker.	jeremybennett	4959d 01h	/openrisc/trunk/
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	4960d 17h	/openrisc/trunk/
411	Improved ethmac testbench and software. Renamed some OR1200 library functions to be more generic. Fixed bug with versatile_mem_ctrl for Actel board. Added ability to simulate gatelevel modules alongside RTL modules in board build.	julius	4961d 05h	/openrisc/trunk/
410	ORPSoC: Adding README in root explaining how to build documentation, and documentation fixup so it builds properly again.	julius	4962d 05h	/openrisc/trunk/
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	4962d 05h	/openrisc/trunk/
408	ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.	julius	4962d 17h	/openrisc/trunk/
407	Update or1ksim version in toolchain script to rc2	julius	4962d 20h	/openrisc/trunk/
406	ORPmon indented files, bus, align and instruction errors vectors printf and reboot	julius	4962d 21h	/openrisc/trunk/

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