OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 441

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
421 Fixing some typos in bld-all.sh's --help printout and changed all
"cd .." lines to "cd -".
julius 4975d 01h /openrisc/trunk/
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 4976d 23h /openrisc/trunk/
419 ORPmon: Fixed interrupt routines in reset.S so they are compatible with new
GCC port (skip over redzone).
Added some defines to easily switch what is done when an error vector
is executed.
Added ability to print out EPCR when crashing.
Changed linker script back to one which doesn't skip over holes in SPI
flash memories.
julius 4977d 02h /openrisc/trunk/
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 4977d 02h /openrisc/trunk/
417 ORPSoC re-adding doc automake files, this time not symlinks julius 4979d 23h /openrisc/trunk/
416 ORPSoC doc cleanup - removing symlinks from automake'd docs build path julius 4979d 23h /openrisc/trunk/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 4979d 23h /openrisc/trunk/
414 Updates to add -mredzone and improved GCC optimizations. jeremybennett 4980d 18h /openrisc/trunk/
413 Fixed to combined bug in the assembler and linker. jeremybennett 4981d 21h /openrisc/trunk/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4983d 13h /openrisc/trunk/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.