URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 462

Rev	Log message	Author	Age	Path
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	4936d 13h	/openrisc/trunk/
441	Changes for gdbserver.	jeremybennett	4936d 20h	/openrisc/trunk/
440	Updated documentation to describe new Ethernet usage.	jeremybennett	4937d 15h	/openrisc/trunk/
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	4939d 19h	/openrisc/trunk/
438	Fix to newlib header and library locations.	jeremybennett	4942d 20h	/openrisc/trunk/
437	Or1ksim - ethernet peripheral update, working much better.	julius	4945d 09h	/openrisc/trunk/
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	4946d 10h	/openrisc/trunk/
435	ORPSoC updates OR1200 multiply/MAC/division unit update with serial multiply and divide options. Full divide not synthesizable yet. New software tests of multiply and divide functionality.	julius	4946d 10h	/openrisc/trunk/
434	Work in progress with new Ethernet TUN/TAP interface.	jeremybennett	4949d 16h	/openrisc/trunk/
433	New single program interrupt test programs.	jeremybennett	4950d 18h	/openrisc/trunk/