URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 499

Rev	Log message	Author	Age	Path
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	4891d 00h	/openrisc/trunk/
478	ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups.	julius	4892d 16h	/openrisc/trunk/
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	4893d 00h	/openrisc/trunk/
476	ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more.	julius	4893d 17h	/openrisc/trunk/
475	ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0.	julius	4893d 20h	/openrisc/trunk/
474	uC/OS-II port linker flags updated.	julius	4894d 01h	/openrisc/trunk/
473	Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux.	jeremybennett	4894d 20h	/openrisc/trunk/
472	Various changes which improve the quality of the tracing.	jeremybennett	4894d 21h	/openrisc/trunk/
471	Adding ucos-ii port.	julius	4897d 00h	/openrisc/trunk/
470	ORPSoC OR1200 crt0 updates.	julius	4897d 20h	/openrisc/trunk/