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Rev Log message Author Age Path
482 Don't hardcode tool versions in help text olof 4891d 03h /openrisc/trunk/
481 OR1200 Update. RTL and spec. julius 4902d 21h /openrisc/trunk/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4903d 19h /openrisc/trunk/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4904d 18h /openrisc/trunk/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4906d 10h /openrisc/trunk/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.
julius 4906d 18h /openrisc/trunk/
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 4907d 11h /openrisc/trunk/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4907d 14h /openrisc/trunk/
474 uC/OS-II port linker flags updated. julius 4907d 20h /openrisc/trunk/
473 Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux. jeremybennett 4908d 14h /openrisc/trunk/

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