OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 672

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
652 Fix make compile.tcl for actel backend yannv 4622d 03h /openrisc/trunk/
651 ORPSoC: The ability to use a free/gimped version of Modelsim was restricted to
the reference build's scripts. This patch adds support for it to the
scripts for the board builds as well.

Signed-off-by: Julius Baxter <julius at opencores.org>
acked-by: Stefan Kristiansson <stefan.kristiansson at saunalahti.fi>
julius 4626d 22h /openrisc/trunk/
650 ORPSoC: documentation update to fix explanation of Xilinx environment setup, add section for Atlys board, various cleanups julius 4627d 19h /openrisc/trunk/
649 porting some of standard demo tasks

fix serial port(UART) interrupt handler
filepang 4644d 01h /openrisc/trunk/
648 docs: OR1K architecture now labeled as revision 0 in draft spec julius 4646d 20h /openrisc/trunk/
647 or1200: update documentation to go with recent rtl commits julius 4646d 21h /openrisc/trunk/
646 Support ORSoC FT4232 board by using second JTAG; should make a command line option. yannv 4650d 07h /openrisc/trunk/
645 or1200: Specification document source now in asciidoc format. ODT and MS Word format documents deprecated, PDF regenerated julius 4664d 20h /openrisc/trunk/
644 or1200: the infamous l.rfe fix, and bug fix for when multiply is disabled julius 4664d 21h /openrisc/trunk/
643 or1200: new ALU comparision implementation option, TLB invalidate register indicated as not present, multiply overflow detection bug fix julius 4664d 21h /openrisc/trunk/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.