URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 75

Rev	Log message	Author	Age	Path
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5329d 15h	/openrisc/trunk/
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5339d 22h	/openrisc/trunk/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5357d 22h	/openrisc/trunk/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5358d 19h	/openrisc/trunk/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5372d 21h	/openrisc/trunk/
50	Adding or32_funcs.S	julius	5373d 01h	/openrisc/trunk/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5391d 15h	/openrisc/trunk/
48	Adds an initialization to keep GCC happy in jp1_ll_read_jp1.	jeremybennett	5391d 18h	/openrisc/trunk/
47	debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions	julius	5401d 01h	/openrisc/trunk/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5407d 02h	/openrisc/trunk/