URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 78

Rev	Log message	Author	Age	Path
58	ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up	julius	5355d 01h	/openrisc/trunk/
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5360d 05h	/openrisc/trunk/
56	adding generic pll model to orpsoc	julius	5368d 07h	/openrisc/trunk/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5370d 21h	/openrisc/trunk/
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5381d 04h	/openrisc/trunk/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5399d 05h	/openrisc/trunk/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5400d 01h	/openrisc/trunk/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5414d 03h	/openrisc/trunk/
50	Adding or32_funcs.S	julius	5414d 08h	/openrisc/trunk/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5432d 21h	/openrisc/trunk/