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Rev Log message Author Age Path
71 ORPSoC board builds, adding readmes julius 5237d 10h /openrisc/trunk/
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5241d 14h /openrisc/trunk/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5241d 15h /openrisc/trunk/
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5244d 07h /openrisc/trunk/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5244d 10h /openrisc/trunk/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5264d 08h /openrisc/trunk/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5268d 14h /openrisc/trunk/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5271d 09h /openrisc/trunk/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5281d 06h /openrisc/trunk/
62 This material is part of the separate website downloads directory. jeremybennett 5292d 09h /openrisc/trunk/

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