URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] - Rev 468

Rev	Log message	Author	Age	Path
448	Changed or32 to openrisc as Linux architecture name.	jeremybennett	4997d 04h	/openrisc/trunk/
447	Updates to register order.	jeremybennett	4997d 22h	/openrisc/trunk/
446	gdb-7.2 gdbserver updates.	julius	4998d 16h	/openrisc/trunk/
445	gdbserver update to use kernel port ptrace register definitions.	julius	4999d 13h	/openrisc/trunk/
444	Changes to ABI handling of varargs.	jeremybennett	4999d 22h	/openrisc/trunk/
443	Work in progress on more efficient Ethernet.	jeremybennett	5000d 02h	/openrisc/trunk/
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	5000d 16h	/openrisc/trunk/
441	Changes for gdbserver.	jeremybennett	5000d 23h	/openrisc/trunk/
440	Updated documentation to describe new Ethernet usage.	jeremybennett	5001d 18h	/openrisc/trunk/
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	5003d 22h	/openrisc/trunk/