URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] - Rev 505

Rev	Log message	Author	Age	Path
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	4912d 03h	/openrisc/trunk/
484	Changes to make r12 call-saved and to bring wchar tests in line.	jeremybennett	4913d 01h	/openrisc/trunk/
483	Updated with new opcodes to generate random numbers and to identify us as Or1ksim.	jeremybennett	4915d 03h	/openrisc/trunk/
482	Don't hardcode tool versions in help text	olof	4916d 15h	/openrisc/trunk/
481	OR1200 Update. RTL and spec.	julius	4928d 10h	/openrisc/trunk/
480	ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.	julius	4929d 07h	/openrisc/trunk/
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	4930d 07h	/openrisc/trunk/
478	ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups.	julius	4931d 22h	/openrisc/trunk/
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	4932d 06h	/openrisc/trunk/
476	ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more.	julius	4933d 00h	/openrisc/trunk/