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[/] [openrisc/] [trunk/] - Rev 85

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Rev Log message Author Age Path
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5290d 08h /openrisc/trunk/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5293d 03h /openrisc/trunk/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5303d 00h /openrisc/trunk/
62 This material is part of the separate website downloads directory. jeremybennett 5314d 03h /openrisc/trunk/
61 The build directory should not be part of the SVN configuration. jeremybennett 5314d 04h /openrisc/trunk/
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5320d 21h /openrisc/trunk/
59 Toolchain install script gcc patch change and gdb configure change julius 5341d 21h /openrisc/trunk/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5344d 20h /openrisc/trunk/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5350d 00h /openrisc/trunk/
56 adding generic pll model to orpsoc julius 5358d 02h /openrisc/trunk/

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