URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] - Rev 143

Rev	Log message	Author	Age	Path
118	New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library.	jeremybennett	5177d 17h	/openrisc/trunk/
117	Updates on l.ff1, l.fl1 and l.maci.	jeremybennett	5179d 20h	/openrisc/trunk/
116	Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time.	jeremybennett	5179d 20h	/openrisc/trunk/
115	Added support for l.fl1 and tests for l.ff1 and l.fl1	jeremybennett	5180d 20h	/openrisc/trunk/
114	l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR.	jeremybennett	5180d 21h	/openrisc/trunk/
113	Updates to exception handling for l.add and l.div	jeremybennett	5181d 20h	/openrisc/trunk/
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5181d 20h	/openrisc/trunk/
111	Changed conditionals for Verilator to "verilator" instead of "VERILATOR".	jeremybennett	5182d 01h	/openrisc/trunk/
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5182d 21h	/openrisc/trunk/
109	or_debug_proxy does signals with signals, just ignores signals	julius	5183d 05h	/openrisc/trunk/