URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] - Rev 208

Rev	Log message	Author	Age	Path
188	More rigorous testing of options.	jeremybennett	5114d 09h	/openrisc/trunk/
187	Or1200 sprs FPU update	julius	5116d 02h	/openrisc/trunk/
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5116d 04h	/openrisc/trunk/
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5116d 05h	/openrisc/trunk/
184	Fix the UART version of newlib.	jeremybennett	5117d 09h	/openrisc/trunk/
183	Fix to setjmp, so it works. Some commenting tidy ups elsewhere.	jeremybennett	5118d 01h	/openrisc/trunk/
182	Removed redundant code.	jeremybennett	5118d 01h	/openrisc/trunk/
181	Updated, so only GCC tries to use parallel build. Redundant target for libgcc removed.	jeremybennett	5118d 04h	/openrisc/trunk/
180	Rewritten to use namespace clean BSP in libgloss. Two versions of the library, one with, one without using the UART.	jeremybennett	5118d 04h	/openrisc/trunk/
179	Code is now loaded from address 0, with section .vectors loaded before any other section. This provides a convenient mechanism for setting up the OR1K exception vectors.	jeremybennett	5118d 04h	/openrisc/trunk/