URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] - Rev 434

Rev	Log message	Author	Age	Path
414	Updates to add -mredzone and improved GCC optimizations.	jeremybennett	5060d 11h	/openrisc/trunk/
413	Fixed to combined bug in the assembler and linker.	jeremybennett	5061d 13h	/openrisc/trunk/
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	5063d 06h	/openrisc/trunk/
411	Improved ethmac testbench and software. Renamed some OR1200 library functions to be more generic. Fixed bug with versatile_mem_ctrl for Actel board. Added ability to simulate gatelevel modules alongside RTL modules in board build.	julius	5063d 17h	/openrisc/trunk/
410	ORPSoC: Adding README in root explaining how to build documentation, and documentation fixup so it builds properly again.	julius	5064d 17h	/openrisc/trunk/
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	5064d 17h	/openrisc/trunk/
408	ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.	julius	5065d 06h	/openrisc/trunk/
407	Update or1ksim version in toolchain script to rc2	julius	5065d 08h	/openrisc/trunk/
406	ORPmon indented files, bus, align and instruction errors vectors printf and reboot	julius	5065d 09h	/openrisc/trunk/
405	ORPmon updates - ethernet driver updates	julius	5065d 13h	/openrisc/trunk/