URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] - Rev 482

Rev	Log message	Author	Age	Path
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	4939d 18h	/openrisc/trunk/
461	Updated to be much stricter about usage.	jeremybennett	4941d 13h	/openrisc/trunk/
460	Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes.	jeremybennett	4941d 14h	/openrisc/trunk/
459	Add option to bld-all.sh to explicitly set control load of make, and fix typos.	julius	4941d 20h	/openrisc/trunk/
458	or1ksim testsuite updates	julius	4942d 19h	/openrisc/trunk/
457	or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again.	julius	4951d 09h	/openrisc/trunk/
456	ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default.	julius	4951d 10h	/openrisc/trunk/
455	Updated to support threads. Does require thread debugging enabled in uClibc.	jeremybennett	4955d 12h	/openrisc/trunk/
454	Updated to incorporate pthreads for Linux tool chain.	jeremybennett	4957d 14h	/openrisc/trunk/
453	Updates to support constructor/destructor initialization for uClibc.	jeremybennett	4958d 01h	/openrisc/trunk/