URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] - Rev 75

Rev	Log message	Author	Age	Path
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5354d 05h	/openrisc/trunk/
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5364d 13h	/openrisc/trunk/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5382d 13h	/openrisc/trunk/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5383d 09h	/openrisc/trunk/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5397d 12h	/openrisc/trunk/
50	Adding or32_funcs.S	julius	5397d 16h	/openrisc/trunk/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5416d 05h	/openrisc/trunk/
48	Adds an initialization to keep GCC happy in jp1_ll_read_jp1.	jeremybennett	5416d 08h	/openrisc/trunk/
47	debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions	julius	5425d 16h	/openrisc/trunk/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5431d 17h	/openrisc/trunk/