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67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5263d 09h /openrisc/trunk/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5283d 07h /openrisc/trunk/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5287d 13h /openrisc/trunk/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5290d 08h /openrisc/trunk/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5300d 05h /openrisc/trunk/
62 This material is part of the separate website downloads directory. jeremybennett 5311d 09h /openrisc/trunk/
61 The build directory should not be part of the SVN configuration. jeremybennett 5311d 09h /openrisc/trunk/
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5318d 02h /openrisc/trunk/
59 Toolchain install script gcc patch change and gdb configure change julius 5339d 02h /openrisc/trunk/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5342d 01h /openrisc/trunk/

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