OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] - Rev 809

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
352 OR1200 RTL DC sensitivity list fix julius 5016d 10h /openrisc/trunk/or1200/rtl/
260 Fixed `define in FPU that didnt need to be there julius 5022d 08h /openrisc/trunk/or1200/rtl/
259 Fixing or1200_defines FPU module selection defines - They are no longer needed julius 5024d 04h /openrisc/trunk/or1200/rtl/
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5024d 04h /openrisc/trunk/or1200/rtl/
187 Or1200 sprs FPU update julius 5074d 08h /openrisc/trunk/or1200/rtl/
186 OR1200 RTL FPU fix - RF writeback signal working properly again julius 5074d 11h /openrisc/trunk/or1200/rtl/
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5074d 12h /openrisc/trunk/or1200/rtl/
151 OR1200 rel3 (added some files that were not checked-in earlier) marcus.erlandsson 5083d 08h /openrisc/trunk/or1200/rtl/
142 added OpenRISC version rel3 marcus.erlandsson 5085d 16h /openrisc/trunk/or1200/rtl/
141 added OpenRISC version rel3 marcus.erlandsson 5085d 16h /openrisc/trunk/or1200/rtl/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.